[Field of the Invention]
The invention relates to a semiconductor device and more particularly relates to a semiconductor device having an electrostatic discharge (ESD) protection capability.
[Description of Related Art]
Electrostatic discharge refers to a phenomenon that charges accumulated in a non-conductor or a non-grounded conductor, and then rapidly discharged through a discharge path in a short time. Electrostatic discharge would cause damage to the circuits in an integrated circuit. For example, a human body, a machine for packaging the integrated circuit, and an instrument for testing the integrated circuit are all common charged bodies. When such a charged body comes in contact with a chip, the charges may be discharged to the chip. An instantaneous power of the electrostatic discharge may damage the integrated circuit in the chip or cause failure.
Considering compatibility with the current CMOS manufacturing process, extended drain MOSFETs (EDMOSFET), lateral double-diffused MOSFETs (LDMOSFET), and reduced surface field (RESURF) are extensively applied to power semiconductor devices. In the field of power semiconductor devices, a MOS having a low on-state resistance is often used as a switch. However, the current only flows through the MOS surface of low on-state resistance, which limits the ESD discharging path. Moreover, a MOS having a high breakdown voltage (BV) also has a higher trigger voltage, and as a result, the risk of damaging the MOS increases. In the field of power semiconductor devices, the aforementioned two aspects impose a great challenge on improvement of the performance of electrostatic discharge protection.